  Codec reset depends re-initializing the memory controller after
the reset.  This is done via a series of qcc writes.  The 
register/value pairs are taken from the same reg file that is used
by the bootloader.  the reg2cmd.c is a utility which is used to 
process a reg file created in the qmmkernel and produce an C table.  
  Unfortunately, this process is not automatic and it must be done
manually if a new reg is used

To compile
cc reg2cmds.c -o reg2cmds

To run
./reg2cmds -i <reg_file> > codec_reset_cmdtable.h

 Do not re-direct stderr to the output file.  Only QCC writes are 
supported so messages for skipped commands will be printed to stderr.  
In addition, all non PMC/MMU register writes must be moved to the 
end of the table, after the last instance of a MMU access but 
before other non-PMC/MMU accesses.
 For example the generated table may look like this

{ QCC_WRITE,    1, 0x0014, 0, 0x00097e7d, 0x00000000 }, /* QDBG_SYS */
{ QCC_WRITE,    3, 0x0014, 0, 0x00097e7c, 0x00000000 }, /* VID      */
{ QCC_WRITE,   18, 0x0008, 2, 0x00000008, 0x00000000 }, /* PMU      */
{ QCC_WRITE,   17, 0x0016, 1, 0x00000035, 0x00000000 }, /* PMC      */
{ QCC_WRITE,   17, 0x0015, 1, 0x00000024, 0x00000000 }, /* PMC      */
.
.
{ QCC_WRITE,   16, 0x0020, 2, 0x00005a2a, 0x00000000 }, /* MMU      */
{ QCC_WRITE,   16, 0x0022, 2, 0x00008000, 0x00000000 }, /* MMU      */
{ QCC_WRITE,   18, 0x02f8, 2, 0x00004001, 0x00000000 }, /* PMU      */
{ QCC_WRITE,   18, 0x02fa, 2, 0x00004001, 0x00000000 }, /* PMU      */

so, all non PMC/MMU register writes must be moved to the
end of the table, after the last instance of a MMU access but
before other non-PMC/MMU accesses would result in this


{ QCC_WRITE,   17, 0x0016, 1, 0x00000035, 0x00000000 }, /* PMC      */
{ QCC_WRITE,   17, 0x0015, 1, 0x00000024, 0x00000000 }, /* PMC      */
.
.
{ QCC_WRITE,   16, 0x0020, 2, 0x00005a2a, 0x00000000 }, /* MMU      */
{ QCC_WRITE,   16, 0x0022, 2, 0x00008000, 0x00000000 }, /* MMU      */
	/* inserted writes, inserted inbetween last MMU and non-MMU command */
{ QCC_WRITE,    1, 0x0014, 0, 0x00097e7d, 0x00000000 }, /* QDBG_SYS */
{ QCC_WRITE,    3, 0x0014, 0, 0x00097e7c, 0x00000000 }, /* VID      */
{ QCC_WRITE,   18, 0x0008, 2, 0x00000008, 0x00000000 }, /* PMU      */
	/* end of inserted writes */
{ QCC_WRITE,   18, 0x02f8, 2, 0x00004001, 0x00000000 }, /* PMU      */
{ QCC_WRITE,   18, 0x02fa, 2, 0x00004001, 0x00000000 }, /* PMU      */



