Porting the SerialICE Kernel

In most cases it will be sufficient to simply change the interrupt number, and possibly the base address of the SIO. The following code fragment, which was taken from the SerialICE Kernel for the BDMR4101 shows where the SIO base address and interrupt input are defined.

	#define UART_BASE 	0xbfff0200
	#define UART_RXS	0x0	/* rx status */
	#define UART_RXC	0x0	/* rx control */
	#define UART_RXHR	0x4	/* rx holding reg */
	#define UART_TXS	0x8	/* tx status */
	#define UART_TXHR	0xc	/* tx holding reg */
	#define UART_INTBIT	SR_INT2

The SIO on this board is connected to INT2, where the following numbering is used.

SR bit number SR bit name Alternate SR bit name CAUSE bit name Description

8 SR_IBIT1 - CAUSE_SW1 Software int1

9 SR_IBIT2 - CAUSE_SW2 Software int2

10 SR_IBIT3 SR_INT0 CAUSE_IP3 Hardware int0

11 SR_IBIT4 SR_INT1 CAUSE_IP4 Hardware int1

12 SR_IBIT5 SR_INT2 CAUSE_IP5 Hardware int2

13 SR_IBIT6 SR_INT3 CAUSE_IP6 Hardware int3

14 SR_IBIT7 SR_INT4 CAUSE_IP7 Hardware int4

15 SR_IBIT8 SR_INT5 CAUSE_IP8 Hardware int5

SR bit number	SR bit name	Alternate SR bit name	CAUSE bit name	Description
8	SR_IBIT1	-	CAUSE_SW1	Software int1
9	SR_IBIT2	-	CAUSE_SW2	Software int2
10	SR_IBIT3	SR_INT0	CAUSE_IP3	Hardware int0
11	SR_IBIT4	SR_INT1	CAUSE_IP4	Hardware int1
12	SR_IBIT5	SR_INT2	CAUSE_IP5	Hardware int2
13	SR_IBIT6	SR_INT3	CAUSE_IP6	Hardware int3
14	SR_IBIT7	SR_INT4	CAUSE_IP7	Hardware int4
15	SR_IBIT8	SR_INT5	CAUSE_IP8	Hardware int5

Note that it is recommended that you do not use the non-maskable interrupt input (even if you have one), because although this will make it possible for the SerialICE Kernel to always get control from the application. It will also make it possible for it to get control at unsafe times, and therefore not be able to resume the application later.

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