//=======================
// PAGE_8 ( FPGA_PHY0 )
//=======================
0x800 0x00050060 //(CCK TXSC=DUP)0x00050000 //0x00050000 (enable watch_dog), [24:25] must be enabled after initialization 
0x804 0x00000005
0x808 0x0000fc00 //0x00000000 (set value for PSD module)
0x80c 0x0000001c //(increase TX power to Pout=13dBm)0x00000003 //(reduce TX power)0x00000007 
0x810 0x801010aa //0x801010a4 //0x801010a5 //(reduce CCK-part)0x801010aa //(For BCM solution)0x80101088 //(for b/g-mode TKIP)0x60101066 //(for 87B)0x40101044 //(RF R->T=2us, below "3" is failed)0x80101088 //(reduce MACTXEN to PHYTXPE=3.6us)0x801010ff //(delay PA starting time at TX)0x202020bb //(increase MACTXen to TXpe duration)0x20202088 (after 061208) //0x08000068 
0x814 0x000908c0 //(reduce CCM_mask to support RIFS)0x002118c0 //(ccamask_ofdm=5.2us, ccamask_intf=2us)0x0018dad0 //0x000018c0 (before 1213) //0x00000000 //0x08000068
0x818 0x00000000 //0x08000068
0x81c 0x00000000 //0x08000068
0x820 0x00000004 
0x824 0x00690000 //(Z4 is without TRSW)0x00690200 //0x00600000 (enable cck highpower)
0x828 0x00000004 
0x82c 0x00e90000 //(for Z4E)(for 8190-B, because RX0 and RX1 are coupling seriously when TX)0x00690000 //(Z4 is without TRSW)0x00690200 //0x00600000 (enable cck highpower)
0x830 0x00000004 
0x834 0x00690000 //(Z4 is without TRSW)0x00690200 //0x00600000 (enable cck highpower)
0x838 0x00000004 
0x83c 0x00e90000 //(for Z4E)(for 8190-B, because RX0 and RX1 are coupling seriously when TX)0x00690000 //(Z4 is without TRSW)0x00690200 //0x00600000 (enable cck highpower)
0x840 0x00000000
0x844 0x00000000 
0x848 0x00000000 
0x84c 0x00000000 
0x850 0x00000000      
0x854 0x00000000 
0x858 0x65a965a9 //(TRSW&TRSWB polarity for RTL8256 E-Cut)0xa965a965  
0x85c 0x65a965a9 //(TRSW&TRSWB polarity for RTL8256 E-Cut)0xa965a965
0x860 0x001f0010 //(RFENV->SW control for Z4-D)0x001f0000 //only 3-wire and RF_ENV output enable//0xffff0130
0x864 0x007f0010 //(TRSW&TRSWB output enable for RTL8256 E-Cut, Path-B)0x001f0010 //(RFENV->SW control for Z4-D)0x001f0000 //only 3-wire and RF_ENV output enable//0xffff0130
0x868 0x001f0010 //(RFENV->SW control for Z4-D)0x001f0000 //only 3-wire and RF_ENV output enable//0xffff0130
0x86c 0x007f0010 //(TRSW&TRSWB output enable for RTL8256 E-Cut, Path-D)0x001f0010 //(RFENV->SW control for Z4-D)0x001f0000 //only 3-wire and RF_ENV output enable//0xffff0130
0x870 0x0f100f70 //(TRSW&TRSWB hardware control for RTL8256 E-Cut, Path-B)0x0f700f70 //(RFENV->SW control for Z4-D)0x0f600f60 //TRSW, PAPE & AntSW software ontrol for Z4
0x874 0x0f100f70 //(TRSW&TRSWB hardware control for RTL8256 E-Cut, Path-D)0x0f700f70 //(RFENV->SW control for Z4-D)0x0f600f60 //TRSW, PAPE & AntSW software ontrol for Z4
0x878 0x00000000
0x87c 0x00000000
0x880 0x5c385eb8 //(for 8190-B)0x1c38deb8 //(disable B/D-path DAC)0x1c38fff8 //0x00000004 //FPGA is for Z1
0x884 0x6357060d //(for 8190-B)0x6357066c //(ADC bias: 0.85->0.75)0xe357066c //(increase CPU)0xe357060c//0xe357060c//0x00000004 //FPGA is for Z1
0x888 0x0460c341 //0x0460c2c1 (DAC=0.461V)//0x0460c341 (DAC=0.546V) //(for 8190-B)0x0c60c340 //(DAC=0.8->0.546V)0x0c60c4c0 //(ADC bias: 0.85->0.75)0x0c60c4c1 //(solve A-path ADC's problem, CLK inverse)0x0460c4c1 //(due to regulator 1.4->1.47)0x0260c4c1 //0x00000004 //FPGA is for Z1
0x88c 0x0000ff00 //(disable AD when TX)0x0000ff0f //(enable DAC10 power saving at RX)0x00000f0f//0x00000004 //FPGA is for Z1
0x890 0x00000000
0x894 0xfffffffe //(add CCX counter)0x00000000
0x898 0x4c42382f //(TH of CCX-NHM)0x40302010                                                                                                                                                                                                                                              
0x89c 0x00656056 //(TH of CCX-NHM)0x00706050       
0x8b0 0x00000000
0x8e0 0x00000000
0x8e4 0x00000000
//
//=======================
// PAGE_9 ( FPGA_PHY1 )
//=======================
0x900 0x00000000 //(RF_mode=1)0x00000000
0x904 0x00000023 
0x908 0x00000000  
0x90c 0x35541545 //(legacy only at ant-C)0x35541555 //(forced TX-A/C)0x33321333 //default: ant-A/B are TX, but in RF-layout, ant-A/C are TX. Config needs change.
//
//=======================
// PAGE_A ( CCK_PHY0 )
//=======================
0xa00 0x00d0c7d8 //(HW antenna switch on)0x00d047d8 //(rx_sub_ch->upper)0x00d047c8//If CCK LBK, 0x00d047cb
0xa04 0xab1f0008 //(RX: default-C, option-D)0xa41f0008 //(RX: default-B, option-A)0xa81f0008 //(for 8190-B cut)0xa81f1008 //(RX in ant-C, CCK TX in both ant-A/C)0x811f1008 //(inverse CCK CLK phase)0x811f0008
0xa08 0x80cd8300 //(avoid 40M-DUP failed!)0x80c88600 //(tight CCA)0x80888600
0xa0c 0x2e62740f //(Set larger RF initial gain for CCK)0x2e62120f 
0xa10 0x95009b78
0xa14 0x11145008 //(improve CCK 1M preamble tracking)0x112e5008 //(CCK_RXHP=10KHz)0xa14 0x112e4008
0xa18 0x00881117
0xa1c 0x89140fa0
0xa20 0x1a1b0000 //(CCK TXAGC, BB_gain=-9dB)0x25260000 //BB:-6dB 0x1b,0x1a,0x17,0x13,0x0e,0x09,0x04,0x02
0xa24 0x090e1317 //(CCK TXAGC, BB_gain=-9dB)0x0d141b21
0xa28 0x00000204 //(CCK TXAGC, BB_gain=-9dB)0x00000306
0xa2c 0x00000000
//
//=======================
// PAGE_C ( OFDM_PHY0 )
//=======================
0xc00 0x00000040 //(shift_L=6)0x00000080 
0xc04 0x0000500f //(10/6dB)0x0000500f //(backoff to 12/6dB)0x0000000f //FPGA:2T2R, 0x00000003 
0xc08 0x000000e4 
0xc0c 0x6c6c6c6c //0x14141414(unsign, offset is defined as positive)
0xc10 0x08000000 //0x00000000(enable DC NF filter)
0xc14 0x40000100
0xc18 0x08000000
0xc1c 0x40000100 //(I/Q needs inverse)0x40000100 
0xc20 0x08000000
0xc24 0x40000100
0xc28 0x08000000
0xc2c 0x40000100 //(I/Q needs inverse)0x40000100 
0xc30 0x6de9ac44 //0x6de98c44 //0x6de98b44 //0x6de98a44 //(win_L for PD=6)0x6de96a44 //(SBD win_L=9)0x8de96a44 //(PWED=2^0)0x8de96c44 //(MF_win_L=5, window_L=9->10)0x6de92c44 //(PDED_TH=2^0)0x6de92d41 //0x6de9cd45 //0x6de98d4b //(tight MF)0x6de98d47 //0x6de9cd49 (version before 0107)
0xc34 0x164052cd //(frame_DC_length=10)0x154052cd //(sub=2) //0x144052cd //0x144030d5  
0xc38 0x00070a14 //(0x14 will degrade MCS=0/1 sensitivity)0x00070a16 //0x00010a10 //0x00010a13  
0xc3c 0x0a969764 //(process_delay=6)0x0a9a9764 //(process_delay=10)0x0a979764 //(PD MF_hold)0x0a97af64 //(modify SGI)0x9e97af64 //(tight DC)0x9e97ab14 //0x9f37ab14 
0xc40 0x1f7c403f //(disable NBI detection)0x1f7c423f //0x007c423f(enable notch filter auto selection) 
0xc44 0x000100b7 //(lookback=4->3)0x000100c7 
0xc48 0xec020000 
0xc4c 0x00000314 //0x00000300(for AP) //0x00000325 //(reduce)0x00000300 //(disable because ch-1)0x00000346 //0x00000358 //(set ED_CCA)0x00000325 //(release ED_CCA condition)0x00000388 //0x00000398 (edcca H-to-L)
0xc50 0x69543420 //0x69543424 //(-74dBm)0x6954341c //(AGC flow=PW_TH)0xe954341c //(-82dBm)0xe9543424 //(initial gain=-74dBm)0xe9543420 //0xeaa03420 //0xe9543420 
0xc54 0x433c0094 //(PW_TH=10dB for AGC flow decision)0x433c0194 //0x00000194
0xc58 0x69543420 //0x69543424 //(-74dBm)0x6954341c //(AGC flow=PW_TH)0xe954341c //(-82dBm)0xe9543424 //(initial gain=-74dBm)0xe9543420 //0xeaa03420 //0xe9543420 
0xc5c 0x433c0094 //(PW_TH=10dB for AGC flow decision)0x433c0194 //0x00000194
0xc60 0x69543420 //0x69543424 //(-74dBm)0x6954341c //(AGC flow=PW_TH)0xe954341c //(-82dBm)0xe9543424 //(initial gain=-74dBm)0xe9543420 //0xeaa03420 //0xe9543420
0xc64 0x433c0094 //(PW_TH=10dB for AGC flow decision)0x433c0194 //0x00000194
0xc68 0x69543420 //0x69543424 //(-74dBm)0x6954341c //(AGC flow=PW_TH)0xe954341c //(-82dBm)0xe9543424 //(initial gain=-74dBm)0xe9543420 //0xeaa03420 //0xe9543420
0xc6c 0x433c0094 //(PW_TH=10dB for AGC flow decision)0x433c0194 //0x00000194
0xc70 0x2c7f000d //(increse rssi_h to 128, avoid AGC_flow=1) 0x2c5a000d //0x2c40aaa5 (version before 1025) 
0xc74 0x0186175b //(RSSI=1000ns, Hssi=200ns)0x01c6175b //(increase RF settling time for D-path)0x018616db //(modify settling time, RSSI & BBP )0x0186151b 
0xc78 0x0000001f
0xc7c 0x00b91612 //(HTAGC freeze=2.5dB)0x00b81612 
0xc80 0x40000100 //(for new TXAGC(MP), TX BB=0dB)0x288000a2 //(TX BB=-4dB)0x40000100 
0xc84 0x00000000 
0xc88 0x40000100 
0xc8c 0x08000000 //(preamble MF weighting opt=2 fail!)0x08200000 //0x20200000 //0x00000000 (before 1221) 
0xc90 0x40000100 //(for new TXAGC(MP), TX BB=0dB)0x288000a2 //(TX BB=-4dB)0x40000100  
0xc94 0x00000000 
0xc98 0x40000100 
0xc9c 0x00000000 
0xca0 0x00492492 //-- TX channel emulator --
0xca4 0x00000000
0xca8 0x00000000
0xcac 0x00000000
0xcb0 0x00000000
0xcb4 0x00000000
0xcb8 0x00000000
0xcbc 0x00492492
0xcc0 0x00000000
0xcc4 0x00000000
0xcc8 0x00000000
0xccc 0x00000000
0xcd0 0x00000000
0xcd4 0x00000000
0xcd8 0x64b22427 //0x64b22326 (old) //-- DFS funciton --
0xcdc 0x00766932 //0x00758d63 (old) 
0xce0 0x00222222 //new 3-bits RXHP setting
//
//=======================
// PAGE_D ( OFDM_PHY1 )
//=======================
0xd00 0x00000740 //(shift_L=6)0x00000780 //(add default ctrl_ch in RF_mode=40M)0x00000380 
0xd04 0x0000040f //FPGA:2T2R, 0x00000403 
0xd08 0x0000803f //(for 8190-B, BB drop agg=0 & HT-length>8K)0x0000003f //0x0000001f (before 1213) //0x000000c7 
0xd0c 0x00000001 //0x00000000
0xd10 0xa0633333 //(S_factor=4/8)0xa0699999 //(S=12/8)0xa0622222 //(csi->average mode)0xa0722222 //(S_factor=3/8)0xa0777777 //0xa0700000(for old s_factor) //0xa0755555 (smaller S_factor) 
0xd14 0x33333c63 //(SBD fine-tune by GI=18)x33333c67 //(S_factor=4/8)0x99993c67 //(S=12/8)0x22223c67 //(S_factor=3/8)0x77773c67 //0x77773c67 //0x00000067(for old s_factor) 
0xd18 0x6a8f5b6b //(disable ch_smooth)0x6a8f5b6f //0x0a8f5b6f(add csi_mask) //0x028f5b6f(for csi_val_gated) //0x020f5b6f (enable antenna weight)
0xd1c 0x00000000
0xd20 0x00000000
0xd24 0x00000000
0xd28 0x00000000
0xd2c 0xcc979975 //(loop_filter=>integral, csi_noise est: average)0xcc9f9974 //for 5G(0xcc9fd974) //0x0c9fd974(for preset_csi_scheme/smooth) //0x0c9f9974 (for fc=2.4G, but FPGA is downrate by 2/4) 
0xd30 0x00000000
0xd34 0x00000000
0xd38 0x00000000
0xd3c 0x00027293 //(reduce TH)0x000272d3 //interference detection disable for sensitivity test 
0xd40 0x00000000
0xd44 0x00000000
0xd48 0x00000000
0xd4c 0x00000000
0xd50 0x6437140a //(add initial state of noise generator)0x00000000
0xd54 0x024dbd02 //(add initial state of noise generator)0x00000000
0xd58 0x00000000
0xd5c 0x14032064 //(new->old, TH=30dB)0x04032064 //(for 8190-B, better postFFT weighting)0x2d432064 //(add weighting scheme)0x00832064 //(add antenna weighting TH)0x00032064
//
//=======================
// PAGE_1 ( Pseudo-MAC )
//=======================
//0x100 0x00000300 // enable BBRSTB, bcz HSSI use clk_bb
//0x114 0x00000003 // debug port selection. 0x0~0x3: PHY DBG, 0x4~0x5: MAC DBG
//0x120 0x08000000 // MAC header-0
//0x124 0xffffffff // MAC header-1
//0x140 0xf3a00001 // Force CCK to be "long-preamble"
//0x14c 0x0000031c //(increase TXAGC)0x00000303 // TXAGC and TXSC setting (sharing with 0x80c and 0x90c)
0xff
