//=========================
// PHY_related MAC register
//=========================
0x03c 0xffff0000 0x0f0f     //0x1818     //(SIFS=24us)default=0x0f0f0000 
//0x320 0xffffffff 0x8f07f000
//0x338 0xffffffff 0x8f07f000 //(skip MCS7)0x0f0f0000 //TX Rate Adaptive, (SGI=8,MCS[27:12],OFDM[11:4],CCK[3:0])
//0x318 0x0000000f 0x1        //FW update TX Rate Adaptive table
0x340 0xffffffff 0x080e0e0f //(for AP power tracking)0x0a0c0d0f //0x080b0b0e //(enhance output power)0x04080808 //0x1c202020 //0x181c1c1c //0x161a1a1a //(for new TXAGC(MP))0x20222222 //0x24242424 //(RFSI suggested)0x22222222 //TXAGC:MCS/rate=(11,10,9,8)=(3,2,1,0)=(24,18,12,9/6)
0x344 0xffffffff 0x03060608 //(for AP power tracking)0x06070809 //0x00050508 //(enhance output power)0x00000204 //0x18181a1c //0x14141618 //0x12121416 //(for new TXAGC(MP))0x18181820 //0x1a1e2224 //(RFSI suggested)0x16192122 //(DAC=0.8V->0.546V)0x161a2222 //TXAGC:MCS/rate=(15,14,13,12)=(7,6,5,4)=(X,54,48,36)
0x348 0x0000ffff 0x0000     //(for new TXAGC(MP))0x1818     //TXAGC:CCK=(11M/5.5M,2M/1M)
//0x12c 0xffffffff 0x08003004 //DIG TH in driver
0x12c 0xffffffff 0x04000802 //0x10004004 //0x10004010 //(reduce DIG_TH)0x40020080 //0x4001b040 //DIG TH in driver
0x318 0x00000fff 0x800 		//0x100      //DIG 100:enable, 800:disable   
0xff
